Most power semiconductor devices such as high-voltage P-I-N diodes and power transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT) have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been used due to their superior properties. III-Nitride (III-N) semiconductor devices are emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage operation, and fast switching times. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1.
Examples of III-N high electron mobility transistors (HEMTs) of the prior art are shown in FIGS. 1 and 2. The III-N HEMT of FIG. 1 includes a substrate 10, a III-N channel layer 11, such as a layer of GaN, atop the substrate, and a III-N barrier layer 12, such as a layer of AlxGa1-xN, atop the channel layer. A two-dimensional electron gas (2DEG) channel 19 is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain contacts 14 and 15, respectively, form ohmic contacts to the 2DEG channel. Gate contact 16 modulates the portion of the 2DEG in the gate region, i.e., directly beneath gate contact 16.
Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT of the prior art is shown in FIG. 2. In addition to the layers included in the device of FIG. 1, the device in FIG. 2 includes a field plate 18 which is connected to gate 16, and an insulator layer 13, such as a layer of SiN, is between the field plate 18 and the III-N barrier layer 12. Field plate 18 can include or be formed of the same material as gate 16. Insulator layer 13 can act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to insulator layer 13.
Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A prior art III-N device similar to that of FIG. 2, but with a slant field plate 24, is shown in FIG. 3. In this device, gate 16 (i.e., the portion of electrode 29 that is between the vertical dashed lines) and slant field plate 24 are formed of a single electrode 29. Electrode-defining layer 23 is an insulating layer, such as SiN, that contains a recess which defines at least in part the shape of electrode 29. Electrode-defining layer 23 can also act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to electrode-defining layer 23. Gate 16 and slant field plate 24 in this device can be formed by first depositing electrode-defining layer 23 over the entire surface of III-N barrier layer 12, then etching a recess through the electrode-defining layer 23 in the region containing gate 16, the recess including a slanted sidewall 25, and finally depositing electrode 29 at least in the recess and over the slanted sidewall 25.
Slant field plates, such as field plate 24 in FIG. 3, tend to spread the electric fields in the device over a larger volume as compared to conventional field plates, such as field plate 18 in FIG. 2, which do not include a slanted portion. Hence, slant field plates tend to be more effective at reducing the peak electric field in the underlying device, thereby allowing for larger operating and breakdown voltages.
The III-N HEMTs shown in FIGS. 1-3 are depletion-mode (i.e., D-mode), or normally-on devices. That is, they are in the ON (conductive) state when 0V is applied to the gate relative to the source and a positive voltage is applied to the drain relative to the source. In order to turn the devices OFF such that they are in a non-conductive state, a sufficiently negative voltage must be applied to the gate relative to the source. In many applications, it is desirable to utilize enhancement-mode (or E-mode) devices, i.e., devices with a positive threshold voltage, as this can simplify the form of the signals applied by the gate-drive circuit to the device and can prevent accidental turn on of the device in case of device or circuit failure.
Reliable fabrication and manufacturing of high-voltage III-N E-mode devices has thus far proven to be very difficult. One prior art alternative to a single high-voltage III-N E-mode device is to combine a high-voltage III-N D-mode device with a low-voltage silicon-based E-mode device in the configuration of FIG. 4 to form a hybrid device, which in many cases achieves the same or similar output characteristics as a single high-voltage E-mode device. The hybrid device of FIG. 4 includes a high-voltage III-N D-mode transistor 5 and a low-voltage silicon-based E-mode transistor 4. Node 1 serves as the source of the hybrid device, node 2 serves as the gate of the hybrid device, and node 3 serves as the drain of the hybrid device. The source electrode of the low-voltage E-mode transistor 4 and the gate electrode of the high-voltage D-mode transistor 5 are both electrically connected to the source node 1. The gate electrode of the low-voltage E-mode transistor 4 is electrically connected to the gate node 2. The drain electrode of the high-voltage D-mode transistor 5 is electrically connected to the drain node 3. The source electrode of the high-voltage D-mode transistor 5 is electrically connected to the drain electrode of the low-voltage E-mode transistor 4. When gate node 2 is biased relative to source node 1 at a voltage higher than the threshold voltage of E-mode transistor 4, the hybrid device is in the ON state, and conducts current between source and drain nodes 1 and 3, respectively, when a positive voltage is applied to the drain node 3 relative to the source node 1. When gate node 2 is biased relative to source node 1 at zero volts or at another voltage which is lower than the threshold voltage of E-mode transistor 4, the hybrid device is in the OFF state. In the OFF state, the hybrid device does not conduct substantial current between source and drain nodes 1 and 3, respectively, when a positive voltage is applied to the drain node 3 relative to the source node 1. In this state, the hybrid device is capable of supporting any drain-source voltages which are less than or equal to the breakdown voltage of the high-voltage D-mode transistor 5.